----------------------------------------------------------------------------------
-- Project 2, Part 2
-- Jason Parrott
-- Rodney McGee
-- Ray
--
-- Main architecture
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity base is
  port ( clk      : in    std_logic;
         reset    : in    std_logic;
         PS2_data : inout std_logic;
         PS2_clk  : inout std_logic;
         LED      : out   std_logic_vector(7 downto 0);
         LCD_D    : out   std_logic_vector (11 downto 8);
         LCD_E    : out   std_logic;
         LCD_RS   : out   std_logic;
         LCD_RW   : out   std_logic;
         rx       : in    std_logic;
         tx       : out   std_logic);
end base;

architecture wrapper of base is

  signal keyboard_ascii : std_logic_vector (7 downto 0);
  signal keyboard_ready : std_logic;
  signal ascii_code     : std_logic_vector (7 downto 0);
  signal lcd_data_ready : std_logic; 


    component LCD_top
      port ( clk            : in  std_logic;
             reset          : in  std_logic;
             keyboard_data  : in  std_logic_vector (7 downto 0);
             keyboard_ready : in  std_logic;
             LCD_D          : out std_logic_vector (11 downto 8);
             LCD_E          : out std_logic;
             LCD_RS         : out std_logic;
             LCD_RW         : out std_logic);
    end component;

  component keyboard_top
    port (
      PS2_data   : inout std_logic;
      PS2_clk    : inout std_logic;
      LED        : out   std_logic_vector(7 downto 0);
      clk        : in    std_logic;
      reset      : in    std_logic;
      data_ready : out   std_logic;
      ascii_out  : out   std_logic_vector (7 downto 0)
      );
  end component; 
    

    component program
      port ( clk            : in  std_logic;
             reset          : in  std_logic;
             keyboard_ascii : in  std_logic_vector (7 downto 0);
             keyboard_ready : in  std_logic;
             ascii_code     : out std_logic_vector (7 downto 0);
             lcd_data_ready : out std_logic;
             leds           : out std_logic_vector(7 downto 0);
             tx             : out std_logic;
             rx             : in  std_logic);
    end component;

begin

  M1 : LCD_top port map(clk, reset, ascii_code, lcd_data_ready, LCD_D, LCD_E, LCD_RS, LCD_RW);
  M2 : Keyboard_top port map(PS2_data, PS2_clk, open, clk, reset, keyboard_ready, keyboard_ascii);
  M3 : program port map(clk => clk, reset => reset, keyboard_ascii => keyboard_ascii, keyboard_ready => keyboard_ready, ascii_code => ascii_code, lcd_data_ready => lcd_data_ready, leds => LED, tx => tx, rx => rx); 
    
end wrapper;
